/*----------------------------------------------------------------------
 *
 * Copyright 2009, Thomas Dejanovic, Jay Shurtz.
 *
 * This is free software; you can redistribute it and/or modify it
 * under the terms of the GNU Lesser General Public License as
 * published by the Free Software Foundation; either version 2.1 of
 * the License, or (at your option) any later version.
 *
 * This software is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this software; if not, write to the Free
 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA, or see the FSF site: http://www.fsf.org.
 *
 *---------------------------------------------------------------------
 *
 * testbench description here
 *
 * NOTE : this is a fairly simple test bench and you should consider
 * setting up a test harness and using that instead.
 *
 *---------------------------------------------------------------------
 * $Id: module_test_template.v 667 2010-07-01 00:12:17Z jayshurtz $
 * $URL: http://hatch.googlecode.com/svn/tags/taggle_release_2.2/tools/templates/module_test_template.v $
 * $Author: jayshurtz $
 *---------------------------------------------------------------------*/

`timescale 1ns/1ns

module MODULE_TEST_NAME ();

  parameter            TESTBENCH_TIMEOUTus = 5000;
  parameter            TEST_NAME = "MODULE_TEST_NAME";

  //----------------------------------------
  reg                 CLK60;
  reg                 reset60;

  reg                 CLK90;
  reg                 reset90;

  reg                 CLK120;
  reg                 reset120;
  //----------------------------------------

  //----------------------------------------
  //

  //----------------------------------------


  /*----------------------------------------------------------------*/

  /*AUTOREG*/

  /*AUTOWIRE*/

  /*------------------------------------------------------------------
   *
   *
   *
   * */

  initial begin
    $display("module name = %s", TEST_NAME);
    $display("vzd file name = %s",{TEST_NAME,".netlist_vzd"});
  end

  initial begin
`ifdef VCD
 `ifdef NETLIST_SIM
  `ifdef VZD
    $dumpfile({TEST_NAME,".netlist_vzd"});
  `else
    $dumpfile({TEST_NAME,".netlist_vcd"});
  `endif
 `else
  `ifdef VZD
    $dumpfile({TEST_NAME,".vzd"});
  `else
    $dumpfile({TEST_NAME,".vcd"});
  `endif
 `endif
    $dumpvars(0);
`endif
  end


  integer              timeout;
  initial begin
    for (timeout=0 ; timeout < TESTBENCH_TIMEOUTus; timeout=timeout+1) #1000;
    $display("*** ERROR - tesbench timeout at %t.", $time);
    // $display("*** not a real test.");
    $finish();
  end

  /*-----------------------------------------------------------------
   *
   *
   *
   * */

  //
  // system clocks.
  //
  reg clk;
  initial clk = 0;
  always #1.4 clk <= ~clk;

  integer CLK60_count, CLK90_count, CLK120_count;
  initial begin
    CLK60        = 0;
    CLK60_count  = 0;
    CLK90        = 0;
    CLK90_count  = 0;
    CLK120       = 0;
    CLK120_count = 0;
  end

  always @ (clk) begin
    if (CLK60_count == 5) begin
      CLK60_count  <= 0;
      CLK60        <= ~CLK60;
    end else
      CLK60_count  <= CLK60_count + 1;

    if (CLK90_count == 3) begin
      CLK90_count  <= 0;
      CLK90        <= ~CLK90;
    end else
      CLK90_count  <= CLK90_count + 1;

    if (CLK120_count == 2) begin
      CLK120_count  <= 0;
      CLK120        <= ~CLK120;
    end else
      CLK120_count  <= CLK120_count + 1;
  end

  /*-----------------------------------------------------------------
   *
   *
   *
   * */

  integer i,j,k;
  initial begin
    reset120  = 1'd1;
    reset90   = 1'd1;
    reset60   = 1'd1;

    for (i=0 ; i<100; i=i+1) @ (posedge CLK60);

    reset120  = 1'd0;
    reset90   = 1'd0;
    reset60   = 1'd0;

    for (i=0 ; i<10; i=i+1) @ (posedge CLK60);

    // do stuff to increace shareholder value :-)

    // $display("*** TEST FINISHED.");
    // $finish();
  end


  /*-----------------------------------------------------------------
   *
   *
   *
   * */




  /*-----------------------------------------------------------------
   *
   *
   *
   * */

  // global reset support for xilinx.
  // glbl glbl ();
  // ini1tial #1 glbl.GSR_int = 0;


  /* MODULE_NAME AUTO_TEMPLATE (
   ) */
  MODULE_NAME dut
    (/*AUTOINST*/);

  /*----------------------------------------------------------------*/

endmodule // MODULE_TEST_NAME

// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
